This invention relates generally to voltage translator circuits and more particularly to a complementary metal oxide semiconductor (CMOS) voltage translator circuit for use with reduced geometry CMOS integrated circuits.
As CMOS devices are implemented with shorter channel lengths in order to achieve faster operation and increase layout density, it becomes necessary to operate these devices at a reduced supply voltage level to avoid channel punch-through. However, usually these reduced geometry circuits must operate with the same higher voltage supply as other devices not subject to this supply voltage limitation. A voltage translator circuit is therefore required on a short channel CMOS integrated device to reduce the supply voltage to a predetermined level.